1. Field of the Invention
The invention relates to nonvolatile memory, and particularly a nonvolatile memory array and cell structure.
2. Description of the Related Art
Non-volatile memory devices of the type commonly referred to in the art as EPROM, EEPROM, or Flash EEPROM serve a variety of purposes, and are hence provided in a variety of architectures and circuit structures. One common application of EEPROMs is in programmable logic devices.
Semiconductor processing technology has moved progressively toward defining smaller device features, characterized by the channel length of transistors in the so-called 0.18 and 0.13 micron processes. As feature sizes shrink, the conventional "stacked gate" EEPROM structure has given way to different cell designs and array architectures, all intended to increase density and reliability in the resulting circuit. In most cases, cell designers strive for designs which are reliable, scalable, cost effective to manufacture and able to operate at lower power, in order for manufacturers to compete in the semiconductor industry. EEPROM designers strive to reduce power requirements of devices by reducing program and erase voltage requirements.
Typically, in programmable logic EEPROM devices, in order to store a logical zero, electrons are injected onto the floating gate to provide a negative voltage on the floating gate thus increasing the control gate threshold voltage needed to turn on the transistor. Conversely, to store a logical one, electrons are removed from the floating gate thereby decreasing the threshold voltage.
One example of a commercially successful EEPROM structure for programmable logic applications is shown in U.S. Pat. No. 4,924,278 (hereinafter "the '278 patent"), issued to Stewart Logie on May 8, 1990 and assigned to the assignee of the present invention.
FIGS. 1 and 2 show a schematic diagram and a cross-section, respectively, of one embodiment of the EEPROM structure shown in the '278 patent. The EEPROM structure disclosed therein utilizes a single layer of polycrystalline silicon and a control gate formed in the silicon substrate to eliminate the need to form a separate control gate and floating gate in layers of polysilicon. The EEPROM structure is made up of three separate NMOS transistors: a write transistor, a read transistor, and a sense transistor. In order to "program" the floating gate, a net positive charge is placed on the gate by removing free electrons from the floating gate. Likewise, to erase the floating gate, the floating gate is given a net negative charge by injecting electrons onto the floating gate.
This EEPROM structure has been well exploited in commercial devices. Nevertheless, as process technologies and practical considerations drive designers toward higher performance, alternative designs are investigated. The aforementioned cell structure requires, in a number of embodiments, a minimum oxide thickness of about 85-100 .ANG. for the program junction oxide region (between the control gate 39 and floating gate 38) due to the presence of the relatively high electric field across the oxide during the life of the cell. In order to accomplish scaling of the device, it would be desirable to provide a design wherein such region could be scaled without performance loss.
In addition, improvements in the quality of the program junction oxide can lead to operational advantages such as lower voltage operation and increased reliability of the device.